XMC4700 / XMC4800 Microcontroller Series for Industrial Applications

XMC4700 / XMC4800 Microcontroller Series for Industrial Applications XMC4000 Family ARM® Cortex®-M4 32-bit processor core Data Sheet V1.1 2018-09 Microcontrol lers

Edition 2018-09 Published by Infineon Technologies AG 81726 Munich, Germany © 2018 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

XMC4700 / XMC4800 Microcontroller Series for Industrial Applications XMC4000 Family ARM® Cortex®-M4 32-bit processor core Data Sheet V1.1 2018-09 Microcontrol lers

XMC4700 / XMC4800 XMC4000 Family XMC4[78]00 Data Sheet Revision History: V1.1 2018-09 Previous Versions: V1.0 2016-01 V0.7 2015-10 (preliminary) Page Subjects 55 Added RMS Noise parameter in VADC Parameters table. 8 Corrected EtherCAT features to 8 Fieldbus Memory Management Units (FMMU) and 8 Sync Manager. 46 Added footnote explaining minimum VBAT requirements to start the hibernate domain and/or oscillation of a crystal on RTC_XTAL. 53 Added HIBIO characteristics. 59 Corrected DAC INL and gain error. 71 Changed frequency dependency of the current consumption. 74 Added peripheral idle current overview. 128ff Updated package parameters and drawings. 133 Higher HBM and CDM ESD limits. Trademarks C166™, TriCore™, XMC™ and DAVE™ are trademarks of Infineon Technologies AG. ARM®, ARM Powered®, Cortex®, Thumb® and AMBA® are registered trademarks of ARM, Limited. CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace Buffer™ are trademarks of ARM, Limited. Synopsys™ is a trademark of Synopsys, Inc. We Listen to Your Comments Is there any information in this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Data Sheet V1.1, 2018-09 Subject to Agreement on the Use of Product Information

XMC4700 / XMC4800 XMC4000 Family Table of Contents Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.1 Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.2 Port I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.2.1 Port I/O Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3 Power Connection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.1.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.1.3 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.1.4 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.1.5 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2.1 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2.2 Analog to Digital Converters (VADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2.3 Digital to Analog Converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.2.4 Out-of-Range Comparator (ORC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.2.5 Die Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.2.6 USB OTG Interface DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.7 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.2.8 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.2.9 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.3.2 Power-Up and Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.3.3 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.3.4 Phase Locked Loop (PLL) Characteristics . . . . . . . . . . . . . . . . . . . . . . 81 3.3.5 Internal Clock Source Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.3.6 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.3.7 Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . . . 86 3.3.8 Embedded Trace Macro Cell (ETM) Timing . . . . . . . . . . . . . . . . . . . . . 87 3.3.9 Peripheral Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Data Sheet 5 V1.1, 2018-09 Subject to Agreement on the Use of Product Information

XMC4700 / XMC4800 XMC4000 Family Table of Contents 3.3.9.1 Delta-Sigma Demodulator Digital Interface Timing . . . . . . . . . . . . . . 88 3.3.9.2 Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . . 89 3.3.9.3 Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.3.9.4 Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.3.9.5 SDMMC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.3.10 EBU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 3.3.10.1 EBU Asynchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 3.3.10.2 EBU Burst Mode Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 3.3.10.3 EBU Arbitration Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.3.10.4 EBU SDRAM Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 3.3.11 USB Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 3.3.12 Ethernet Interface (ETH) Characteristics . . . . . . . . . . . . . . . . . . . . . . . 119 3.3.12.1 ETH Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . 119 3.3.12.2 ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) . . 120 3.3.12.3 ETH MII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 3.3.12.4 ETH RMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 3.3.13 EtherCAT (ECAT) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 3.3.13.1 ECAT Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . 123 3.3.13.2 ETH Management Signal Parameters (MCLK, MDIO) . . . . . . . . . . 123 3.3.13.3 MII Timing TX Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 3.3.13.4 MII Timing RX Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 3.3.13.5 Sync/Latch Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.1.1 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Data Sheet 6 V1.1, 2018-09 Subject to Agreement on the Use of Product Information

XMC4700 / XMC4800 XMC4000 Family About this Document About this Document This Data Sheet is addressed to embedded hardware and software developers. It provides the reader with detailed descriptions about the ordering designations, available features, electrical and physical characteristics of the XMC4[78]00 series devices. The document describes the characteristics of a superset of the XMC4[78]00 series devices. For simplicity, the various device types are referred to by the collective term XMC4[78]00 throughout this manual. XMC4000 Family User Documentation The set of user documentation includes: • Reference Manual – decribes the functionality of the superset of devices. • Data Sheets – list the complete ordering designations, available features and electrical characteristics of derivative devices. • Errata Sheets – list deviations from the specifications given in the related Reference Manual or Data Sheets. Errata Sheets are provided for the superset of devices. Attention: Please consult all parts of the documentation set to attain consolidated knowledge about your device. Application related guidance is provided by Users Guides and Application Notes. Please refer to http://www.infineon.com/xmc4000 to get access to the latest versions of those documents. Data Sheet 7 V1.1, 2018-09 Subject to Agreement on the Use of Product Information

XMC4700 / XMC4800 XMC4000 Family Summary of Features 1 Summary of Features The XMC4[78]00 devices are members of the XMC4000 Family of microcontrollers based on the ARM Cortex-M4 processor core. The XMC4000 is a family of high performance and energy efficient microcontrollers optimized for Industrial Connectivity, Industrial Control, Power Conversion, Sense & Control. EtherCAT System System SCU Masters Slaves CPU RTC ARM Cortex-M4 ERU0 GPDMA0 GPDMA1 Ethernet USB WDT OTG System DCode ICode FCE Bus Matrix Data Code PMU PSRAM DSRAM1 DSRAM2 EBU ROM & Flash USIC0 DSD POSIF1 CCU80 CCU81 LEDTS0 CCU43 PORTS DAC PBA0 Peripherals 0 Peripherals 1 PBA1 ERU1 VADC POSIF0 CCU40 CCU41 CCU42 SDMMC USIC2 USIC1 MultiCAN Figure 1 System Block Diagram CPU Subsystem • CPU Core – High Performance 32-bit ARM Cortex-M4 CPU – 16-bit and 32-bit Thumb2 instruction set – DSP/MAC instructions – System timer (SysTick) for Operating System support • Floating Point Unit • Memory Protection Unit • Nested Vectored Interrupt Controller • General Purpose DMA with up-to 12 channels • Event Request Unit (ERU) for programmable processing of external and internal service requests • Flexible CRC Engine (FCE) for multiple bit error detection Data Sheet 8 V1.1, 2018-09 Subject to Agreement on the Use of Product Information

XMC4700 / XMC4800 XMC4000 Family Summary of Features On-Chip Memories • 16 KB on-chip boot ROM • 96 KB on-chip high-speed program memory • 128 KB on-chip high speed data memory • 128 KB on-chip high-speed communication memory • 2,048 KB on-chip Flash Memory with 8 KB instruction cache Communication Peripherals • Ethernet MAC module capable of 10/100 Mbit/s transfer rates • EtherCATSlave interface (ECAT) capable of 100 Mbit/s transfer rates with 2 MII ports, 8 Fieldbus Memory Management Units (FMMU), 8 Sync Manager, 64 bit distributed clocks • Universal Serial Bus, USB 2.0 host, Full-Speed OTG, with integrated PHY • Controller Area Network interface (MultiCAN), Full-CAN/Basic-CAN with 6 nodes, 256 message objects (MO), data rate up to 1 MBaud • Six Universal Serial Interface Channels (USIC),providing 6 serial channels, usable as UART, double-SPI, quad-SPI, IIC, IIS and LIN interfaces • LED and Touch-Sense Controller (LEDTS) for Human-Machine interface • SD and Multi-Media Card interface (SDMMC) for data storage memory cards • External Bus Interface Unit (EBU) enabling communication with external memories and off-chip peripherals Analog Frontend Peripherals • Four Analog-Digital Converters (VADC) of 12-bit resolution, 8 channels each, with input out-of-range comparators • Delta Sigma Demodulator with four channels, digital input stage for A/D signal conversion • Digital-Analog Converter (DAC) with two channels of 12-bit resolution Industrial Control Peripherals • Two Capture/Compare Units 8 (CCU8) for motor control and power conversion • Four Capture/Compare Units 4 (CCU4) for use as general purpose timers • Two Position Interfaces (POSIF) for servo motor positioning • Window Watchdog Timer (WDT) for safety sensitive applications • Die Temperature Sensor (DTS) • Real Time Clock module with alarm support • System Control Unit (SCU) for system configuration and control Input/Output Lines • Programmable port driver control module (PORTS) • Individual bit addressability Data Sheet 9 V1.1, 2018-09 Subject to Agreement on the Use of Product Information

XMC4700 / XMC4800 XMC4000 Family Summary of Features • Tri-stated in input mode • Push/pull or open drain output mode • Boundary scan test support over JTAG interface On-Chip Debug Support • Full support for debug features: 8 breakpoints, CoreSight, trace • Various interfaces: ARM-JTAG, SWD, single wire trace 1.1 Ordering Information The ordering code for an Infineon microcontroller provides an exact reference to a specific product. The code “XMC4<DDD>-<Z><PPP><T><FFFF>” identifies: • <DDD> the derivatives function set • <Z> the package variant – E: LFBGA – F: LQFP – Q: VQFN • <PPP> package pin count • <T> the temperature range: – F: -40°C to 85°C – K: -40°C to 125°C • <FFFF> the Flash memory size. For ordering codes for the XMC4[78]00 please contact your sales representative or local distributor. This document describes several derivatives of the XMC4[78]00 series, some descriptions may not apply to a specific product. Please see Table 1. For simplicity the term XMC4[78]00 is used for all derivatives throughout this document. 1.2 Device Types These device types are available and can be ordered through Infineon’s direct and/or distribution channels. Table 1 Synopsis of XMC4[78]00 Device Types Derivative1) Package Flash SRAM Kbytes Kbytes XMC4700-E196x2048 PG-LFBGA-196 2048 352 XMC4700-F144x2048 PG-LQFP-144 2048 352 XMC4700-F100x2048 PG-LQFP-100 2048 352 XMC4700-E196x1536 PG-LFBGA-196 1536 276 Data Sheet 10 V1.1, 2018-09 Subject to Agreement on the Use of Product Information

XMC4700 / XMC4800 XMC4000 Family Summary of Features Table 1 Synopsis of XMC4[78]00 Device Types (cont’d) Derivative1) Package Flash SRAM Kbytes Kbytes XMC4700-F144x1536 PG-LQFP-144 1536 276 XMC4700-F100x1536 PG-LQFP-100 1536 276 XMC4800-E196x2048 PG-LFBGA-196 2048 352 XMC4800-F144x2048 PG-LQFP-144 2048 352 XMC4800-F100x2048 PG-LQFP-100 2048 352 XMC4800-E196x1536 PG-LFBGA-196 1536 276 XMC4800-F144x1536 PG-LQFP-144 1536 276 XMC4800-F100x1536 PG-LQFP-100 1536 276 XMC4800-E196x1024 PG-LFBGA-196 1024 200 XMC4800-F144x1024 PG-LQFP-144 1024 200 XMC4800-F100x1024 PG-LQFP-100 1024 200 1) x is a placeholder for the supported temperature range. 1.3 Device Type Features The following table lists the available features per device type. Table 2 Features of XMC4[78]00 Device Types Derivative1) LED SD EBU ETH ECAT USB USIC MultiCAN TS MMC Intf.2) Intf. Slave Intf. Chan. Nodes, Intf. Intf. 3) Intf. MO XMC4700-E196x2048 1 1 SDM MR - 1 3 x 2 N[0..5] MO[0..255] XMC4700-F144x2048 1 1 SDM MR - 1 3 x 2 N[0..5] MO[0..255] XMC4700-F100x2048 1 1 M16 R - 1 3 x 2 N[0..5] MO[0..255] XMC4700-E196x1536 1 1 SDM MR - 1 3 x 2 N[0..5] MO[0..255] XMC4700-F144x1536 1 1 SDM MR - 1 3 x 2 N[0..5] MO[0..255] XMC4700-F100x1536 1 1 M16 R - 1 3 x 2 N[0..5] MO[0..255] Data Sheet 11 V1.1, 2018-09 Subject to Agreement on the Use of Product Information

XMC4700 / XMC4800 XMC4000 Family Summary of Features Table 2 Features of XMC4[78]00 Device Types (cont’d) Derivative1) LED SD EBU ETH ECAT USB USIC MultiCAN TS MMC Intf.2) Intf. Slave Intf. Chan. Nodes, Intf. Intf. 3) Intf. MO XMC4800-E196x2048 1 1 SDM MR 2 x 1 3 x 2 N[0..5] MII MO[0..255] XMC4800-F144x2048 1 1 SDM MR 2 x 1 3 x 2 N[0..5] MII MO[0..255] XMC4800-F100x2048 1 1 M16 R 2 x 1 3 x 2 N[0..5] MII MO[0..255] XMC4800-E196x1536 1 1 SDM MR 2 x 1 3 x 2 N[0..5] MII MO[0..255] XMC4800-F144x1536 1 1 SDM MR 2 x 1 3 x 2 N[0..5] MII MO[0..255] XMC4800-F100x1536 1 1 M16 R 2 x 1 3 x 2 N[0..5] MII MO[0..255] XMC4800-E196x1024 1 1 SDM MR 2 x 1 3 x 2 N[0..5] MII MO[0..255] XMC4800-F144x1024 1 1 SDM MR 2 x 1 3 x 2 N[0..5] MII MO[0..255] XMC4800-F100x1024 1 1 M16 R 2 x 1 3 x 2 N[0..5] MII MO[0..255] 1) x is a placeholder for the supported temperature range. 2) Memory types supported S=SDRAM, D=DEMUX, M=MUX 16-bit and 32-bit, M16=MUX 16-bit 3) Supported interfaces, M=MII, R=RMII. Table 3 Features of XMC4[78]00 Device Types Derivative1) ADC DSD DAC CCU4 CCU8 POSIF Chan. Chan. Chan. Slice Slice Intf. XMC4700-E196x2048 32 4 2 4 x 4 2 x 4 2 XMC4700-F144x2048 32 4 2 4 x 4 2 x 4 2 XMC4700-F100x2048 24 4 2 4 x 4 2 x 4 2 XMC4700-E196x1536 32 4 2 4 x 4 2 x 4 2 XMC4700-F144x1536 32 4 2 4 x 4 2 x 4 2 XMC4700-F100x1536 24 4 2 4 x 4 2 x 4 2 XMC4800-E196x2048 32 4 2 4 x 4 2 x 4 2 Data Sheet 12 V1.1, 2018-09 Subject to Agreement on the Use of Product Information

XMC4700 / XMC4800 XMC4000 Family Summary of Features Table 3 Features of XMC4[78]00 Device Types (cont’d) Derivative1) ADC DSD DAC CCU4 CCU8 POSIF Chan. Chan. Chan. Slice Slice Intf. XMC4800-F144x2048 32 4 2 4 x 4 2 x 4 2 XMC4800-F100x2048 24 4 2 4 x 4 2 x 4 2 XMC4800-E196x1536 32 4 2 4 x 4 2 x 4 2 XMC4800-F144x1536 32 4 2 4 x 4 2 x 4 2 XMC4800-F100x1536 24 4 2 4 x 4 2 x 4 2 XMC4800-E196x1024 32 4 2 4 x 4 2 x 4 2 XMC4800-F144x1024 32 4 2 4 x 4 2 x 4 2 XMC4800-F100x1024 24 4 2 4 x 4 2 x 4 2 1) x is a placeholder for the supported temperature range. 1.4 Definition of Feature Variants The XMC4[78]00 types are offered with several memory sizes and number of available VADC channels. Table 4 describes the location of the available Flash memory, Table 5 describes the location of the available SRAMs, Table 6 the available VADC channels. Table 4 Flash Memory Ranges Total Flash Size Cached Range Uncached Range 1,024 Kbytes 0800 0000H − 0C00 0000H − 080F FFFFH 0C0F FFFFH 1,536 Kbytes 0800 0000H − 0C00 0000H − 0817 FFFFH 0C17 FFFFH 2,048 Kbytes 0800 0000H − 0C00 0000H − 081F FFFFH 0C1F FFFFH Data Sheet 13 V1.1, 2018-09 Subject to Agreement on the Use of Product Information

XMC4700 / XMC4800 XMC4000 Family Summary of Features Table 5 SRAM Memory Ranges Total SRAM Size Program SRAM System Data SRAM Communication Data SRAM 200 Kbytes 1FFE E000H − 2000 0000H − − 1FFF FFFFH 2001 FFFFH 276 Kbytes 1FFE 8000H − 2000 0000H − 2002 0000H − 1FFF FFFFH 2001 FFFFH 2002 CFFFH 352 Kbytes 1FFE 8000H − 2000 0000H − 2002 0000H − 1FFF FFFFH 2001 FFFFH 2003 FFFFH Table 6 ADC Channels1) Package VADC G0 VADC G1 VADC G2 VADC G3 PG-LQFP-144 CH0..CH7 CH0..CH7 CH0..CH7 CH0..CH7 PG-LFBGA-196 PG-LQFP-100 CH0..CH7 CH0..CH7 CH0..CH3 CH0..CH3 1) Some pins in a package may be connected to more than one channel. For the detailed mapping see the Port I/O Function table. 1.5 Identification Registers The identification registers allow software to identify the marking. Table 7 XMC4700 Identification Registers Register Name Value Marking SCU_IDCHIP 0004 7001H EES-AA, ES-AA, AA JTAG IDCODE 101D F083H EES-AA, ES-AA, AA Table 8 XMC4800 Identification Registers Register Name Value Marking SCU_IDCHIP 0004 8001H EES-AA, ES-AA, AA JTAG IDCODE 101D F083H EES-AA, ES-AA, AA Data Sheet 14 V1.1, 2018-09 Subject to Agreement on the Use of Product Information

XMC4700 / XMC4800 XMC4000 Family General Device Information 2 General Device Information This section summarizes the logic symbols and package pin configurations with a detailed list of the functional I/O mapping. 2.1 Logic Symbols VAREF VAGND VDDA VSSA VDDC VDDP VSS (1) (1) (1) (1) (4) (4) (1) VBAT (1) Exp. Die Pad (VSS) RTC_XTAL1 (1) VSSO RTC_XTAL2 Port 0 HIB_IO_0 16 bit HIB_IO_1 Port 1 16 bit XTAL1 XTAL2 Port 2 16 bit USB_DP Port 3 USB_DM 16 bit VBUS Port 4 8 bit Port 14 14 bit Port 5 12 bit Port 15 12 bit Port 6 7 bit PORST TCK JTAG ETM / SWD 3 bit 5 / 1 bit TMS via Port Pins Figure 2 XMC4[78]00 Logic Symbol PG-LQFP-144 Data Sheet 15 V1.1, 2018-09 Subject to Agreement on the Use of Product Information

XMC4700 / XMC4800 XMC4000 Family General Device Information VAREF VAGND VDDA VSSA VDDC VDDP VSS (1) (1) (1) (1) (3) (3) (8) VBAT (1) (1) VSSO RTC_XTAL1 Port 0 16 bit RTC_XTAL2 Port 1 HIB_IO_0 16 bit Port 2 HIB_IO_1 16 bit Port 3 XTAL1 16 bit XTAL2 Port 4 8 bit USB_DP Port 5 USB_DM 12 bit VBUS Port 6 7 bit Port 7 Port 14 12 bit 14 bit Port 8 Port 15 12 bit 12 bit Port 9 12 bit PORST TCK JTAG ETM / SWD 3 bit 5 / 1 bit TMS via Port Pins Figure 3 XMC4[78]00 Logic Symbol PG-LFBGA-196 Data Sheet 16 V1.1, 2018-09 Subject to Agreement on the Use of Product Information

XMC4700 / XMC4800 XMC4000 Family General Device Information VAREF VAGND VDDA VSSA VDDC VDDP VSS (1) (1) (1) (1) (4) (4) (1) V Exp. Die Pad BAT (1) (VSS) RTC_XTAL1 (1) VSSO RTC_XTAL2 Port 0 HIB_IO_0 13 bit HIB_IO_1 Port 1 16 bit XTAL1 XTAL2 Port 2 13 bit USB_DP Port 3 USB_DM 7 bit VBUS Port 4 2 bit Port 14 14 bit Port 5 4 bit Port 15 4 bit PORST TCK JTAG SWD 3 bit 1 bit TMS via Port Pins Figure 4 XMC4[78]00 Logic Symbol PG-LQFP-100 Data Sheet 17 V1.1, 2018-09 Subject to Agreement on the Use of Product Information

XMC4700 / XMC4800 XMC4000 Family General Device Information 2.2 Pin Configuration and Definition The following figures summarize all pins, showing their locations on the four sides of the different packages. P0.1 1 108 P1.4 P0.0 2 107 P1.5 P0.10 3 106 P1.10 P0.9 4 105 P1.11 P3.2 5 104 P1.12 P3.1 6 103 P1.13 P3.0 7 102 P1.14 P3.13 8 101 P6.0 P3.12 9 100 P6.1 P3.11 10 99 P6.2 P3.10 11 98 P6.3 P3.9 12 97 P6.4 P3.8 13 96 P6.5 P3.7 14 95 P6.6 USB_DM 15 94 P1.15 USB_DP 16 93 TCK VBUS 17 92 TMS VDDP 18 XMC4[78]00 91 P ORST VDDC 19 90 V DDC HIB_IO _1 20 (Top View) 89 V SSO HIB_IO _0 21 88 X TAL2 RTC_XTAL2 22 87 X TAL1 RTC_XTAL1 23 86 V DDP VBAT 24 85 V SS P15.7 25 84 P5.0 P15.6 26 83 P5.1 P15.5 27 82 P5.2 P15.4 28 81 P5.3 P15.3 29 80 P5.4 P15.2 30 79 P5.5 P14.15 31 78 P5.6 P14.14 32 77 P5.7 P14.13 33 76 P2.6 P14.12 34 75 P2.7 P14.7 35 74 P2.0 P14.6 36 73 P2.1 Figure 5 XMC4[78]00 PG-LQFP-144 Pin Configuration (top view) Data Sheet 18 V1.1, 2018-09 Subject to Agreement on the Use of Product Information P14.5 37 144 P0.2 P14.4 38 143 P0.3 P14.3 39 142 P0.4 P14.2 40 141 P0.5 P14.1 41 140 P0.6 P14.0 42 139 P0.11 P15.15 43 138 P0.12 P15.14 44 137 P0.13 VAGND 45 136 P0.14 VAREF 46 135 P0.15 VSSA 47 134 P3.14 VDDA 48 133 P3.15 P15.13 49 132 P3.3 P15.12 50 131 P3.4 P14.9 51 130 P3.5 P14.8 52 129 P3.6 P15.9 53 128 P0.7 P15.8 54 127 P0.8 P5.11 55 126 VDDP P5.10 56 125 VDDC P 5.9 57 124 P4.0 P 5.8 58 123 P4.1 P2.15 59 122 P4.2 P2.14 60 121 P4.3 VDDC 61 120 P4.4 VDDP 62 119 P4.5 P2.13 63 118 P4.6 P2.12 64 117 P4.7 P2.11 65 116 P1.6 P2.10 66 115 P1.7 P 2.9 67 114 P1.8 P 2.8 68 113 P1.9 P 2.5 69 112 P1.0 P 2.4 70 111 P1.1 P 2.3 71 110 P1.2 P 2.2 72 109 P1.3

XMC4700 / XMC4800 XMC4000 Family General Device Information 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A VSS P8.6 P8.8 P8.10 P8.9 P8.11 P8.1 P9.8 P9.7 P9.9 P9.5 P9.4 n.c. VSS A B n.c. P8.3 P8.2 P8.7 P8.5 P8.4 P8.0 P9.10 P9.11 n.c. P9.6 n.c. VSS n.c. B C VSS VDDC P0.2 P0.3 P0.5 P0.6 P3.6 P0.8 P4.1 P1.8 VDDP VSS n.c. n.c. C D VDDP P3.1 P3.2 P0.10 P0.4 P3.5 P0.7 P4.0 P1.6 P1.7 P1.9 VDDC P9.3 P9.2 D E P3.0 P3.13 P0.1 P0.0 P0.13 P0.15 P4.4 P4.6 P4.7 P1.4 P1.2 P1.3 n.c. P9.1 E USB_D F M P3.12 P3.11 P0.9 P0.12 P3.14 P3.15 P4.5 P1.0 P1.5 P1.11 P1.10 P9.0 P7.11 F USB_D G P VBUS P3.8 P3.7 P0.11 P0.14 P3.4 P4.2 P1.1 P1.14 P1.12 P1.13 P7.9 P7.10 G RTC_X RTC_X HIB_I HIB_I H H TAL1 TAL2 O_1 O_0 P3.9 P3.10 P3.3 P4.3 P6.1 P6.4 P6.5 P6.6 n.c. P7.8 J VBAT P15.3 P15.5 P15.4 P15.6 P15.7 TMS TCK P6.3 P6.0 PORST P1.15 n.c. P7.7 J K P15.2 P14.15 P14.14 P14.13 P5.10 P5.8 P5.2 P5.1 P5.0 P6.2 XTAL1 XTAL2 n.c. P7.6 K L P14.12 P14.7 P14.6 P14.3 P5.11 P2.15 P5.7 P5.5 P2.6 P5.3 P2.0 VSSO P7.0 P7.5 L M P14.4 P14.5 P14.2 P15.15 P15.12 P5.9 P2.14 P5.6 P2.7 P5.4 P2.2 P2.1 P7.1 P7.3 M N VDDA P14.1 P14.0 P15.14 P14.9 P15.9 P2.12 P2.10 P2.8 P2.4 P2.3 VDDP P7.2 P7.4 N P VSSA VAGND VAREF P15.13 P14.8 P15.8 P2.13 P2.11 P2.9 P2.5 VDDC VSS n.c. VSS P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 XMC4[78]00 ‐ (top view) Figure 6 XMC4[78]00 PG-LFBGA-196 Pin Configuration (top view) Data Sheet 19 V1.1, 2018-09 Subject to Agreement on the Use of Product Information

XMC4700 / XMC4800 XMC4000 Family General Device Information P0.1 1 75 P1.4 P0.0 2 74 P1.5 P0.10 3 73 P1.10 P0.9 4 72 P1.11 P3.2 5 71 P1.12 P3.1 6 70 P1.13 P3.0 7 69 P1.14 USB_DM 8 68 P1.15 USB_DP 9 67 TCK VBUS 10 66 TMS VDDP 11 65 PORST VDDC 12 HIB_IO _1 13 XMC4[78]00 64 VDDC 63 VSSO HIB_IO _0 14 62 XTAL2 RTC_XTAL2 15 (Top View) 61 XTAL1 RTC_XTAL1 16 60 VDDP VBAT 17 59 VSS P15.3 18 58 P5.0 P15.2 19 57 P5.1 P14.15 20 56 P5.2 P14.14 21 55 P5.7 P14.13 22 54 P2.6 P14.12 23 53 P2.7 P14.7 24 52 P2.0 P14.6 25 51 P2.1 Figure 7 XMC4[78]00 PG-LQFP-100 Pin Configuration (top view) Data Sheet 20 V1.1, 2018-09 Subject to Agreement on the Use of Product Information P14.5 26 100 P0.2 P14.4 27 99 P0.3 P14.3 28 98 P0.4 P14.2 29 97 P0.5 P14.1 30 96 P0.6 P14.0 31 95 P0.11 VAGND 32 94 P0.12 VAREF 33 93 P3.3 VSSA 34 92 P3.4 VDDA 35 91 P3.5 P14.9 36 90 P3.6 P14.8 37 89 P0.7 P15.9 38 88 P0.8 P15.8 39 87 VDDP P2.15 40 86 VDDC P2.14 41 85 P4.0 VDDC 42 84 P4.1 VDDP 43 83 P1.6 P2.10 44 82 P1.7 P2.9 45 81 P1.8 P2.8 46 80 P1.9 P2.5 47 79 P1.0 P2.4 48 78 P1.1 P2.3 49 77 P1.2 P2.2 50 76 P1.3