Digital IO　M2p.75xx 32チャネル, 125MS/s

M2p多用途用DIO M2p.75xx 32チャネル ～125MS/s ・32デジタル I/O チャネル ・サンプリングスピード 1kS/s ～ 125MS/s ・PCI Express x4 インタフェース ・110Ω 入力インピーダンス選択可 ・3.3V and 5.0V TTL 入力 ・オンボードメモリ 1GByte ・700 MB/s FIFO モード ・16カードまでの同期接続可能 製品名 DIチャネル DOチャネル サンプリング ロジックレベル 周波数 M2p.7515-x4 32 32 125MHz 3.3V / 5V TTL

M2p.75xx-x4 - 32 channel digital I/O card • 32 digital I/O channels • 1 kS/s up to 125 MS/s sampling speed • Ultra Fast PCI Express x4 interface • 110 Ohm input impedance selectable • Inputs 3.3 V and 5.0 V TTL compatible • 1 GByte of on-board memory • 700 MB/s FIFO mode for input and output • Synchronization of up to 16 cards per system • Features: Single-Shot, Streaming, Multiple Recording/Replay, Gated Sampling/Replay, Sequence Mode, Timestamps • Direct data transfer to CUDA GPU using SCAPP option • PCIe x4 Gen 1 Interface • Works with x4/x8/x16* PCIe slots • Sustained streaming mode up to 700 MB/s** • Half-length PCIe Form Factor Operating Systems Recommended Software Drivers • Windows 7 (SP1), 8, 10, • Visual C++, Delphi, C++ Builder, • MATLAB Server 2008 R2 and newer GNU C++, VB.NET, C#, Java, • LabVIEW • Linux Kernel 2.6, 3.x, 4.x, 5.x Python, Julia • Windows/Linux 32 and 64 bit • SBench 6 Input Output General Information Model 16 bit 32 bit 16 bit 32 bit The M2p.75xx series of fast digital I/O cards allow to acquire or replay digital M2p.7515-x4 125 MS/s 125 MS/s 125 MS/s 125 MS/s patterns with a programmable speed of up to 125 MS/s. The direction can be switched by software between input (digital data acquisition) and output (digital pattern generation). The on-board memory of 1 GByte can be completely used for digital pattern. Furthermore the on-board memory can be switched to a FIFO buf- fer allowing to continuously stream data in either output or input direction. Using the unique M2p-Star-Hub up to 16 different cards of the M2p series can be synchronized in one system. The M2p series offers - besides the M2p.75x digital I/O card - 16 bit digitizers with 5 MS/s to 125 MS/s sampling speed and up to 8 channels and 16 bit AWGs with 40 MS/s to 125 MS/s sampling speed and up to 8 channels. *Some x16 PCIe slots are for the use of graphic cards only and can’t be used for other cards.**Throughput measured with a motherboard chipset supporting a TLP size of 256 bytes. SPECTRUM INSTRUMENTATION GMBH · AHRENSFELDER WEG 13-17 · 22927 GROSSHANSDORF · GERMANY 22.4.2021 PHONE: +49 (0)4102-6956-0 · FAX: +49 (0)4102-6956-66 · E-MAIL: info@spec.de · INTERNET: www.spectrum-instrumentation.com

building blocks for basic functions like filtering, averaging, data de- multiplexing, data conversion or FFT. All the software is based on Software Support C/C++ and can easily be implemented, expanded and modified with normal programming skills. Windows drivers The cards are delivered with drivers for Windows 7, Windows 8 General Hardware features and options and Windows 10 (each 32 bit and 64 bit). Programming exam- ples for Visual C++, C++ Builder, Delphi, Visual Basic, VB.NET, PCI Express x4 C#, Python, Java and Julia are included. The M2p series cards use a PCI Express x4 Gen 1 connection. They can be used Linux Drivers in PCI Express x4, x8 and x16 slots with All cards are delivered with full Linux support. Pre com- hosts supporting Gen 1, Gen 2, Gen 3 or piled kernel modules are included for the most common Gen4. The maximum sustained data trans- distributions like Fedora, Suse, Ubuntu LTS or Debian. The fer rate is more than 700 MByte/s (read direction) or 700 MByte/s Linux support includes SMP systems, 32 bit and 64 bit (write direction) per slot. Physically supported slots that are electri- systems, versatile programming examples for GNU C++, cally connected with only x1 or x2 can also be used with the M2p Python as well as the possibility to get the kernel driver sources for series cards, but with reduced data transfer rates. your own compilation. External clock I/O SBench 6 Using a dedicated line a sampling clock can be fed in from an ex- A base license of SBench 6, the ternal system. It’s also possible to output the internally used sam- easy-to-use graphical operating pling clock to synchronize external equipment to this clock. software for Spectrum cards, is in- cluded in the delivery. The base li- Reference clock cense makes it is possible to test The option to use a precise the card, display acquired data external reference clock and make some basic measure- (typically 10 MHz) is nec- ments. It's a valuable tool for essary to synchronize the checking the card’s performance instrument for high-quality and assisting with the unit’s initial measurements with external equipment (like a signal source). It’s setup. The cards also come with a demo license for the SBench 6 also possible to enhance the stability of the sampling clock in this professional version. This license gives the user the opportunity to way. The driver automatically generates the requested sampling test the additional features of the professional version with their clock from the fed in reference clock. hardware. The professional version contains several advanced measurement functions, such as FFTs and X/Y display, import and Star-Hub export utilities as well as support for all acquisition modes including data streaming. Data streaming allows the cards to continuously ac- The Star-Hub is an additional mod- quire data and transfer it directly to the PC RAM or hard disk. ule allowing the phase stable syn- SBench 6 has been optimized to handle data files of several chronization of up to 16 boards in GBytes. SBench 6 runs under Windows as well as Linux (KDE, one system. Two versions are avail- GNOME and Unity) operating systems. A test version of SBench 6 able: one with up to 6 cards and can be downloaded directly over the internet and can run the pro- the large version supports up to 16 fessional version in a simulation mode without any hardware in- cards in one system. Both versions stalled. Existing customers can also request a demo license for the can be mounted in two different professional version from Spectrum. More details on SBench 6 can ways, to either extend the cards be found in the SBench 6 data sheet. length to ¾ PCIe length occupying one slot, or extend its width to two slots whilst keeping the ½ PCIe length. Third-party products Independent of the number of boards Spectrum supports the most popular third-party software products there is no phase delay between the such as LabVIEW or MATLAB. All drivers come with detailed docu- channels. The Star-Hub distributes trigger mentation and working examples are included in the delivery. and clock information between all boards. As a result all connected boards SCAPP – CUDA GPU based data processing are running with the same clock and the For applications requiring same trigger. All trigger sources can be high performance signal combined with OR/AND. For digitizers and data processing that means all channels of all cards to be Spectrum offers SCAPP trigger source at the same time. (Spectrum’s CUDA Access for Parallel Processing). The SCAPP SDK allows a Multi-Purpose I/O direct link between Spec- trum digitizers, AWGs or As standard each card has 4 multi-purpose I/O lines. All I/O lines Digital Data Acquisition can be used for asynchronous digital I/O, can carry additional Cards and CUDA based GPU cards. Once in the GPU users can status information or can be used as trigger inputs. harness the processing power of the GPU’s multiple (up to 5000) processing cores and large (up to 24 GB) memories. SCAPP uses an RDMA (Linux only) process to send data at the full PCIe transfer speed to and from the GPU card. The SDK includes a set of exam- ples for interaction between the Spectrum card and the GPU card and another set of CUDA parallel processing examples with easy

Input (Digital Data Acquisition) features or until a stop command is executed. The trigger source can be ei- ther one of the external trigger inputs or the software trigger. After Ring buffer mode the first trigger additional trigger events will be ignored. The ring buffer mode is the standard mode of all oscillo- Single Restart replay scope instruments. Digitized When this mode is activated the data of the on-board memory will data is continuously written be replayed once after each trigger event. The trigger source can into a ring memory until a be either the external TTL trigger or software trigger. trigger event is detected. After the trigger, post-trigger samples are recorded and pre-trigger samples can also be stored. The number FIFO mode of pre-trigger samples available simply equals the total ring mem- The FIFO or streaming mode is designed for continuous data trans- ory size minus the number of post trigger samples. fer between the card and the PC memory. When mounted in a PCI Express x4 Gen 1 interface both, read and write streaming speeds FIFO mode of up to 700 MByte/s are possible. The control of the data stream The FIFO or streaming mode is designed for continuous data trans- is done automatically by the driver on interrupt request basis. The fer between the card and the PC memory. When mounted in a PCI complete installed on-board memory is used to buffer the data, mak- Express x4 Gen 1 interface both, read and write streaming speeds ing the continuous streaming process extremely reliable. of up to 700 MByte/s are possible. The control of the data stream is done automatically by the driver on interrupt request basis. The Multiple Replay complete installed on-board memory is used to buffer the data, mak- The Multiple Replay mode al- ing the continuous streaming process extremely reliable. lows the fast output genera- tion on several trigger events Multiple Recording without restarting the hard- The Multiple Recording ware. With this option very mode allows the recording of fast repetition rates can be several trigger events with an achieved. The on-board memory is divided into several segments of extremely short re-arming the same size. Each segment can contain different data which will time. The hardware doesn’t then be played with the occurrence of each trigger event. need to be restarted in be- tween. The on-board memory is divided in several segments of the Gated Replay same size. Each of them is filled with data if a trigger event occurs. The Gated Sampling mode al- Pre- and posttrigger of the segments can be programmed. The num- lows data replay controlled ber of acquired segments is only limited by the used memory and by an external gate signal. is unlimited when using FIFO mode. Data is only replayed if the gate signal has attained a Gated Sampling programmed level. The Gated Sampling mode allows data recording con- Sequence Mode trolled by an external gate The sequence signal. Data is only record- mode allows to ed if the gate signal has a split the card programmed level. In addi- memory into sev- tion a pre-area before start eral data segments of different length. These data segments are of the gate signal as well as a post area after end of the gate signal chained up in a user chosen order using an additional sequence can be acquired. The number of gate segments is only limited by memory. In this sequence memory the number of loops for each seg- the used memory and is unlimited when using FIFO mode. ment can be programmed and trigger conditions can be defined to proceed from segment to segment. Using the sequence mode it is Timestamp also possible to switch between replay waveforms by a simple soft- The timestamp function ware command or to redefine waveform data for segments simulta- writes the time positions of neously while other segments are being replayed. All trigger- the trigger events in an extra related and software-command-related functions are only working memory. The timestamps are on single cards, not on star-hub-synchrnonized cards. relative to the start of record- ing, a defined zero time, ex- ternally synchronized to a radio clock, an IRIG-B a GPS receiver. Using the external synchronization gives a precise time relation for acquisitions of systems on different locations. Output (Pattern Generation) features Singleshot output When singleshot output is activated the data of the on-board mem- ory is played exactly one time. The trigger source can be either one of the external trigger inputs or the software trigger. After the first trigger additional trigger events will be ignored. Repeated output When the repeated output mode is used the data of the on-board memory is played continuously for a programmed number of times

Technical Data Power Up Data channels direction after power up input (high impedance) Clock and trigger output after power up disabled Digital Data Inputs Direction software programmable all channels input or all channels output (no mixed direction) Acquisition channel selection software programmable 16 or 32 Sampling clock edge software programmable rising or falling edge (see clock section for details) Logic type 3.3V LVTTL (5V TTL tolerant) with bus-hold as floating input protection Input transition rise or fall rate 10 ns/V Input Impedance software programmable 110  / 50 k || 15 pF 110 termination voltage 2.25 V Standard input levels Low: 0.8 V High: 2.0 V Absolute maximum Input levels Low: 0.5 V High: 7.0 V Input current sink no termination Low: -5.0µA (0.0 V) High:+5.0µA (3.3V), +20.0µA (5.0V) Digital Data Outputs Direction software programmable all channels input or all channels output (no mixed direction) Replay channel selection software programmable 16 or 32 Update clock edge software programmable rising or falling edge (see clock section for details) Logic type 3.3V LVTTL Typical output levels high impedance Low: 0.2 V High: 2.8 V Output max current load Low: 64 mA High: -32 mA Output levels at max load Low: < 0.5 V High: > 2.0 V Output Impedance (typical) ca. 7  Stop level software programmable Tristate, Low, High, Hold Last, Custom Value Output Data Delays Trigger to 1st sample 78 samples Gate end to last replayed sample 78 samples Trigger Available trigger modes software programmable External, Software, Or/And, Delay Trigger edge software programmable Rising edge, falling edge or both edges Trigger pulse width software programmable 0 to [4G - 1] samples in steps of 1 sample Trigger delay software programmable 0 to [4G - 1] samples in steps of 1 samples Trigger holdoff (for Multi, ABA, Gate) software programmable 0 to [4G - 1] samples in steps of 1 samples Multi, ABA, Gate: re-arming time  40 samples (+ programmed pretrigger + programmed holdoff) Pretrigger at Multi, ABA, Gate, FIFO software programmable 8 up to [32 kSamples / number of active channels] in steps of 8 Posttrigger software programmable 8 up to [8G - 4] samples in steps of 8 (defining pretrigger in standard scope mode) Memory depth software programmable 16 up to [installed memory / number of active channels] samples in steps of 8 Multiple Recording/ABA segment size software programmable 8 up to [installed memory / number of active channels] samples in steps of 8 Internal/External trigger accuracy 1 sample (sampled with programmed clock edge, see clock section for details) Timestamp modes software programmable Standard, Startreset, external reference clock on X1 (e.g. PPS from GPS, IRIG-B) Data format Std., Startreset: 64 bit counter, increments with sample clock (reset manually or on start) RefClock: 24 bit upper counter (increment with RefClock) 40 bit lower counter (increments with sample clock, reset with RefClock) Extra data software programmable none, acquisition of X0/X1/X2/X3 inputs at trigger time, trigger source (for OR trigger) Size per stamp 128 bit = 16 bytes External trigger sources X0, X1, X2, X3 External trigger logic type 3.3V LVTTL (5V TTL tolerant) Input transition rise or fall rate 10 ns/V External trigger impedance software programmable 110  / 50 k || 15 pF 110 termination voltage 2.25 V Standard input levels Low: 0.8 V High: 2.0 V Absolute maximum Input levels Low: 0.5 V High: 7.0 V Input current sink no termination Low: -5.0µA (0.0 V) High:+5.0µA (3.3V), +20.0µA (5.0V) External trigger bandwidth 125 MHz Minimum external trigger pulse width 2 samples

Multi Purpose I/O lines Number of multi purpose input/output lines four, named X0, X1, X2, X3 Multi Purpose line X0, X1, X2, X3 Input: available signal types software programmable Asynchronous Digital-In, Timestamp Reference Clock, Logic trigger Input: logic type 3.3V LVTTL (5V TTL tolerant) Input transition rise or fall rate 10 ns/V Input: impedance software programmable 110  / 50 k || 15 pF Input: 110 termination voltage 2.25 V Input: standard levels Low: 0.8 V High: 2.0 V Input: absolute maximum levels Low: 0.5 V High: 7.0 V Input current sink no termination Low: -5.0µA (0.0 V) High:+5.0µA (3.3V), +20.0µA (5.0V) Input: maximum bandwidth 125 MHz Output: available signal types software programmable Run-, Arm-, Trigger-Output, Asynchronous Digital-Out Output: logic type 3.3V LVTTL Output: typical levels high impedance Low: 0.2 V High: 2.8 V Output: max current load Low: 64 mA High: -32 mA Output: levels at max load Low: < 0.5 V High: > 2.0 V Output: impedance (typical) ca. 7  Output: update rate (synchronous modes) sampling clock (on programmed clock edge, see clock section for details) Clock Clock Modes software programmable internal PLL, external clock, external reference clock, sync Active clock edge software programmable rising or falling edge Internal clock range (PLL mode) software programmable 1 kS/s to 125 MS/s Internal clock accuracy after warm-up ±1.0 ppm (at time of calibration in production) Internal clock aging ±0.5 ppm / year PLL clock setup granularity (int. or ext. reference) 1 Hz External reference clock range software programmable 128 kHz up to 125 MHz Direct external clock to internal clock delay 5.0 ns Direct external clock range DC to 125 MHz Direct external clock minimum LOW/HIGH time 4 ns Clock input: logic type 3.3V LVTTL (5V TTL tolerant) Clock input: transition rise or fall rate 10 ns/V Clock input: impedance software programmable 110  / 50 k || 15 pF Clock input: 110 termination voltage 2.25 V Clock input: standard levels Low: 0.8 V, High: 2.0 V Clock input: absolute maximum levels Low: 0.5 V, High: 7.0 V Clock input: current sink (no termination) no termination Low: -5.0µA (0.0 V), High:+5.0µA (3.3V), +20.0µA (5.0V) External reference clock input duty cycle 45% - 55% Clock output: logic type 3.3V LVTTL Clock output: typical levels high impedance Low: 0.2 V, High: 2.8 V Clock output: max current load Low: 64 mA, High: -32 mA Clock output: levels at max load Low: < 0.5 V, High: > 2.0 V Clock output: impedance (typical) ca. 7  Synchronization clock multiplier „N“ for software programmable N being a multiplier (1, 2, 3, 4, 5, ... Max) of the card with the currently slowest sampling clock. different clocks on synchronized cards The card maximum sampling rate must not be exceeded. Connectors Digital Inputs/Outputs 40 pole half pitch (Hirose FX2 series) Cable-Type: Cab-d40-xx-xx Connector on card: Hirose FX2B-40PA-1.27DSL Flat ribbon cable connector: Hirose FX2B-40SA-1.27R Environmental and Physical Details Dimension (Single Card) type 8 channel AWG or L x H x W: 168 mm (½ PCIe length) x 107 mm x 30 mm. Requires one additional slot right of M2p.65x3, M2p.65x8, M2p.654x or M2p.657x High power AWG the main card’s bracket, on „component side“ of the PCIe card. Dimension (all other single cards) L x H x W: 168 mm (½ PCIe length) x 107 mm x 20 mm (single slot width) Dimension (with -SH6tm or -SH16tm installed) Extends W by 1 slot right of the main card’s bracket, on „component side“ of the PCIe card. Dimension (with -SH6ex or -SH16ex installed) Extends L to 245 mm (¾ PCIe length) at the back of the PCIe card Dimension (with -DigSMB or -DigFX2 installed) Extends W by 1 slot left of the main card’s bracket, on „solder side“ of the PCIe card. Weight (M2p.59xx, M2p.75xx series) maximum 215 g Weight (M2p.65x0, M2p.65x1, M2p.65x6 series) maximum 195 g Weight (M2p.65x3, 65x8, 654x, 657x series) maximum 305 g Weight (Star-Hub Option -SH6ex, -SH6tm) including 6 sync cables 65 g Weight (Star-Hub Option -SH16ex, -SH16tm) including 16 sync cables 90 g Weight (Option -DigSMB) 50 g Weight (Option -DigFX2) 60 g Warm up time 10 minutes Operating temperature 0 °C to 40 °C Storage temperature -10 °C to 70 °C Humidity 10% to 90% Dimension of packing 1 or 2 cards 470 mm x 250 mm x 130 cm Volume weight of packing 1 or 2 cards 4 kgs

PCI Express specific details PCIe slot type x4, Generation 1 PCIe slot compatibility (physical) x4, x8, x16 PCIe slot compatibility (electrical) x1, x2, x4, x8, x16 with Generation 1, Generation 2, Generation 3, Generation 4 Sustained streaming mode > 700 MB/s (measured with a chipset supporting a TLP size of 256 bytes, using PCIe x4 Gen1) (Card-to-System: M2p.59xx or M2p.75xx) Sustained streaming mode > 700 MB/s (measured with a chipset supporting a TLP size of 256 bytes, using PCIe x4 Gen1) (System-to-Card: M2p.65xx or M2p.75xx) Certification, Compliance, Warranty EMC Immunity Compliant with CE Mark EMC Emission Compliant with CE Mark Product warranty 5 years starting with the day of delivery Software and firmware updates Life-time, free of charge Power Consumption 3.3V 12V Total M2p.75xx TBD A TBD A TBD W MTBF MTBF TBD hours Clock to data timing The setup and hold times as well as any delays relate to the output clock. Please be sure to meet this timing constraints if feeding in external clock. All timings shown here are in relation to the programmed clock edge (rising or falling). The illustration on the right shows the relation to the rising edge as an example. For detailed information on the different modes for external clocking please refer to the dedicated chapter in the hardware manual for the boards of the M2p.75xx series. Input Parameter External Clocking Internal Clocking (direct and reference clock) Clock Input to Clock Output (single card) td 9.3 ns n.a. Clock In to Clock Out (Star-Hub connected) td TBD n.a. Data/Trigger Output tco1 0.0 ns 0.0 ns tco2 2.0 ns 2.0 ns Data/Trigger Input ts 6.1 ns 6.1 ns th -3.5 ns -3.5 ns When using external clock, a delayed clock signal is generated on the Clock Output pin. The timing data in relation to this delayed clock output is identical to the timing when using internal clocking. It is therefore strongly recommended that you use the delay clock output for clocking any external devices.

Hardware block diagram

Order Information The card is delivered with 1 GByte on-board memory and supports standard acquisition and replay (scope, single-shot, loop, single restart), FIFO acquisition/replay (streaming), Multiple Recording/Replay, Gated Sampling/Replay, Timestamps and Sequence Mode. Operating sys- tem drivers for Windows/Linux 32 bit and 64 bit, examples for C/C++, LabVIEW (Windows), MATLAB (Windows and Linux), .NET, Delphi, Java, Python and a Base license of the oscilloscope software SBench 6 are included. One digital connecting cable Cab-d40-idc-100 is included in the delivery for every digital connection (each 16 channels). PCI Express x4 Order no. Input Output Speed M2p.7515-x4 32 Channels 32 Channels 125 MS/s Options Order no. Option M2p.xxxx-SH6ex (1) Synchronization Star-Hub for up to 6 cards incl. cables, only one slot width, card length 245 mm M2p.xxxx-SH6tm (1) Synchronization Star-Hub for up to 6 cards incl. cables, two slots width, standard card length M2p.xxxx-SH16ex (1) Synchronization Star-Hub for up to 16 cards incl. cables, only one slot width, card length 245 mm M2p.xxxx-SH16tm (1) Synchronization Star-Hub for up to 16 cards incl. cables, two slots width, standard card length M2p-upgrade Upgrade for M2p.xxxx: Later installation of options Star-Hub Cables Option Cab-d40-idc-100 Flat-ribbon cable to 2x20 pole IDC, 100 cm Cab-d40-d40-100 Flat-ribbon cable to 40 pole FX2, 100 cm Software SBench6 Order no. SBench6 Base version included in delivery. Supports standard mode for one card. SBench6-Pro Professional version for one card: FIFO mode, export/import, calculation functions SBench6-Multi Option multiple cards: Needs SBench6-Pro. Handles multiple synchronized cards in one system. Volume Licenses Please ask Spectrum for details. Software Options Order no. SPc-RServer Remote Server Software Package - LAN remote access for M2i/M3i/M4i/M4x/M2p cards SPc-SCAPP Spectrum’s CUDA Access for Parallel Processing - SDK for direct data transfer between Spectrum card and CUDA GPU. Includes RDMA activation and examples. (1) : Just one of the options can be installed on a card at a time. (2) : Third party product with warranty differing from our export conditions. No volume rebate possible. Technical changes and printing errors possible SBench, digitizerNETBOX and generatorNETBOX are registered trademarks of Spectrum Instrumentation GmbH. Microsoft, Visual C++, Windows, Windows 98, Windows NT, Window 2000, Windows XP, Windows Vista, Windows 7, Windows 8 and Windows 10 are trademarks/registered trademarks of Microsoft Corporation. LabVIEW, DASYLab, Diadem and LabWindows/CVI are trademarks/registered trademarks of National Instruments Corporation. MATLAB is a trademark/registered trademark of The Mathworks, Inc. Delphi and C++Builder are trademarks/registered trademarks of Embarcadero Technologies, Inc. Keysight VEE, VEE Pro and VEE OneLab are trademarks/registered trademarks of Keysight Technologies, Inc. FlexPro is a registered trademark of Weisang GmbH & Co. KG. PCIe, PCI Express and PCI-X and PCI-SIG are trademarks of PCI-SIG. LXI is a registered trademark of the LXI Consortium. PICMG and CompactPCI are trademarks of the PCI Industrial Computation Manufacturers Group. Oracle and Java are registered trademarks of Oracle and/or its affiliates. Intel and Intel Core i3, Core i5, Core i7, Core i9 and Xeon are trademarks and/or registered trademarks of Intel Corporation. AMD, Opteron, Sempron, Phenom, FX, Ryzen and EPYC are trademarks and/or registered trademarks of Advanced Micro Devices. NVIDIA, CUDA, GeForce, Quadro and Tesla are trademarks/registered trademarks of NVIDIA Corporation.